1. Field of the Invention
The present invention relates to a layout method and apparatus for integrated circuits (hereinafter, “LSI”), and more particularly to an LSI layout method and layout apparatus, for performing cell arrangement, in which timing is prioritized, and for generating wiring between cells.
2. Description of the Related Art
LSI design is typically conducted using a computer. Particularly in the case of an ASIC (Application Specific Integrated Circuit), which is a semicustom LSI, logic design is conducted for LSIs that are to exhibit target functions, and the layout of the LSI is carried out on the basis of this logic design data. In logic design, essential basic cells are selected from a cell library stored beforehand, whereby a logic circuit is designed to implement the target functions. As a result, logic data (a so-called “net list”) is generated that has a plurality of cells and connections between input/output terminals of these cells. In accordance with this netlist, a layout step is performed for the arrangement of cells on a chip and the generation of connection wiring between these cells.
Upon completion of the layout step, a signal propagation delay time is calculated from the cell drive capability, and the connection wiring resistance, capacitance and inductance, for example, and, by referencing the netlist and delay time, logic simulation is performed. If the result of the logic simulation is a pass, the generation of the actual layout data and the generation of pattern data follow, and then data required for an LSI preliminary step is generated.
An increase in the speeds of LSIs in recent years has been accompanied by the implementation of cell arrangement processing that takes into account signal and clock timing, and optimization processing to optimize the timing of signals and clocks. Particularly in cell automated arrangement processing on the basis of a netlist, an order of priority is determined in which cells are ordered according to an increasing strictness in the timing of input signals and clocks, and the automated arrangement of cells is performed in accordance with this order of priority.
However, due to the great importance placed on the timing of signals and clocks in the arrangement of cells, localized dense regions of cells are sometimes formed on the chip. In other words, a lot of cells are sometimes arranged in regions close to input signal terminals and clock input terminals. As a result, in an automated wiring step, which follows the automated cell arrangement step, on account of the congestion of wiring in these dense regions, there have been frequent cases in which it becomes impossible to generate wiring in these regions. When wiring becomes impossible in the automated wiring step, it is necessary to repeat the automated cell arrangement processing and automated wiring processing, after changing timing conditions or other conditions.
Gate numbers in ASICs of recent years have reached high levels, such that, even when high-speed computers are used, several days are required for the automated cell arrangement processing and automated wiring processing. This means that the above-mentioned repetition of the automated cell arrangement processing and automated wiring processing is not only to be associated with an extension of the ASIC design step and increased costs, but also a loss of the short delivery times that characterize ASICs.